Friday, October 16, 2015 - 2:00pm
Location:Reddy Conference Room 4405 Gates & Hillman Centers
Speaker:BRIAN RAILING, College of Computing http://www.cc.gatech.edu/~brailing/
For More Information, Contact:rosemary @ cs.cmu.edu
Computer architecture has looming challenges with finding program parallelism, process technology limits, and the constrained power budget. To navigate these challenges, a deeper understanding of parallel programs is required. I will describe how representing parallel programs with task graphs can meet this challenge, and particularly by using a compiler-based instrumentation framework. This framework, Contech, is designed for high performance generation of dynamic task graphs from diverse parallel programs, such as those written in C or Fortran and using pthreads, OpenMP, MPI, or Cilk. I will conclude with examples of analyzing Contech task graphs.
Brian Railing is a Ph.D. candidate in Computer Science at Georgia Institute of Technology, under the supervision of Professor Thomas Conte. He received his B.S. in Computer Science from Carnegie Mellon University in 2004. He previously worked for Microsoft analyzing and improving the performance of the Windows kernel before entering graduate studies at Georgia Institute of Technology. His current work is on accurately representing and analyzing parallel programs using Contech.